1. Field of the Invention
The present invention relates to semiconductor memories, and, in particular, to non-volatile, Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable and Programmable Read-Only Memory (EEPROM).
2. Prior Art
Metal Oxide Semiconductor (MOS) semiconductor memory devices, in particular, floating gate MOS transistor structures used as memory cells, are well-known in the art. In general, such devices operate by charging or discharging a floating gate, which floating gate then affects whether the device will easily conduct or will not easily conduct current from drain to source of the MOS transistor. The status of the floating gate as either electrically charged or discharged, which controls the conductance of the channel of the MOS device so that the device can be tested to identify a storage state, makes the device useful in the same fashion as other bi-stable data storage devices such as magnetic cores, flip-flops, and so forth. Memory arrays made of such devices are programmed to one state or the other depending upon the memory storage requirement for each particular cell. By choosing an appropriate convention for an EEPROM, a "0", for example, may be represented as the presence of conduction or, at least relatively high conduction through a cell, and a "1" as the absence of conduction, or relatively low conduction, through a cell, or vice-a-versa.
In EEPROM devices, two mechanisms are generally used for electrically charging or discharging the floating gate: Fowler-Nordheim tunneling and channel hot-electron injection. By Fowler-Nordheim tunneling, the floating gate is charged or discharged by use of a relatively high potential across a thin dielectric layer such as silicon dioxide, causing tunneling of electrons onto or out of the floating gate.
By applying suitable voltages to the gate, drain and source, channel hot electron injection can be made to occur when the channel is near pinch-off, causing an increase in the number of "hot" or high energy electrons, some of which have sufficient energy to transit the insulation layer barrier which separates the channel, from the floating gate. Charges on the floating gate remain after the programming conditions are removed due to the insulation layer such as silicon dioxide which surrounds it.
To make a useful device from the single memory cell which has been described, a plurality of such cells is arranged into rows and columns, groups of drains of memory cells generally being connected by lines called a "bitlines" and groups of gates of memory cells being connected by lines called "wordlines". Each individual cell within the array can be addressed, and its contents can be read-out, by applying appropriate signals to the selected bitline and wordline associated with that particular cell. When so addressed, the existence of charge (or its absence) on the floating gate is determined by interrogating the cell individually and sensing whether it is conductive or non-conductive between the source and the drain. In practical arrays, the individual bits are not read out singly, but are rather read out as bytes: groups of eight related bits.
The geometry of a conventional EPROM cell comprises a channel disposed between drain and source. Overlying the channel and isolated from it by a thin insulating layer is a floating gate. The floating gate is sandwiched between the channel and a select gate and isolated from them by insulating layers. A contact on the drain provides for connection to the bit-line. A wordline extends to each cell. A source line is common to a group of cells. Adjacent cells are isolated by thick field oxide. Such a cell requires space for the contact and the thick field oxide regions which occupy substantial, expensive "real estate" on the silicon substrate.
Recently, EPROM/EEPROM cells which do not require field oxide and contacts were reported. (See, for example, R. Kazerounian, et al.; IEDM Technical Digest Papers, paper 11.5.1, pp 311-314, (1991) or B. J. Woo, et al.; IEDM Technical Digest Papers, paper 5.1.1, pp 91-94, (1990). or Yoshimitsu Yamauchi:, et al; IEDM91, pp 319 to 322.)
Gill, U.S. Pat. No. 5,051,796, issued Sep. 24, 1991, describes buried bitline construction of memory arrays.
Such buried bitlines offer many improvements in construction over the earlier structures, and can provide a theoretically higher density than cells having contacts, in that the area occupied by the cell is reduced by the absence of the metallic contact. However, the buried bitline has high capacitance and, in particular, causes high drain-to-gate capacitance. This causes a reduction in the immunity of the cells to spurious signals which frequently occur during programming.
As memory storage size demands increase, the demands for miniaturization of each individual cell increase correspondingly, the goal being ever-expanding capacity in ever-decreasing physical size, while the cost per bit remains steady or, preferably, decreases. To increase the chip density, the individual cell size must be decreased through various methods such as eliminating contacts, replacing field oxide isolation by junction isolation, and the like. To further reduce cell size, the capacitance coupling ratio of the floating gate to the control gate must be increased, and the control and select methods must be made more reliable.